In advanced logic and memory applications using Complementary Metal Oxide Semiconductor (CMOS) technology (such as static random access memory or SRAM), an Off Chip Driver (OCD) driver circuit may be provided. The OCD is coupled to a system bus that is shared with other components that are also coupled to the same bus.
CMOS is the most widely used technology for integrated circuits today. A CMOS device is a compound device including at least one P-Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET or PFET) and at least one N-Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET or NFET). Typically, one NFET is coupled between the output node and the ground, and one PFET is coupled between the output node and the power supply voltage VDD. Each of NFETs and PFETs includes a metal (or polysilicon) gate electrode, a doped silicon channel, and an oxide dielectric layer separating the gate electrode from the channel.
In a system having a mixed signal interface, the various CMOS devices that are coupled to the system bus may operate at a variety of voltage levels. For example, the power supply voltage VDD for a static random access memory (SRAM) may be 1.8 Volts, while another device coupled to the bus may operate at a voltage up to about 5 volts, depending on the type of device.
Protecting the thin dielectric gate electrode films from an over-voltage condition is desirable when the CMOS device interfaces to a bus that is also coupled to other devices which operate at higher voltages. Otherwise, severe device degradation and gate oxide failure may result. Gate dielectric time to breakdown is a function of oxide thickness, over-voltage magnitude and duty cycle, junction temperature, number of chip power on hours (POH), and the total oxide area exposed to the over voltage stress. This dielectric breakdown is one of the major causes of device failure for CMOS devices.
FIG. 5 corresponds to FIG. 1 of U.S. Pat. No. 4,782,250 issued to Adams et al. (hereinafter referred to as "Adams et al."). Adams et al. describe a CMOS Off-Chip Driver (OCD) fabricated in a 3.3 Volt technology (VDD=3.3 Volts), with a 4.5 Volt (V) maximum gate stress limit on its 150 Angstrom thick gate oxide. This limit is due to a silicon dioxide limit of 3 megavolts per centimeter (MV/cm). This OCD is capable of interfacing to a 5.0 Volt Transistor-Transistor (TTL) bus (not shown) via data output 24. That is, the low voltage 3.3 V OCD and a higher voltage 5.0 V device both interface to a common bus. In this mixed voltage technology/mixed voltage interface environment, the 3.3 Volt OCD can provide a logic-high signal having a magnitude of 3.3.+-.10% V when it controls the bus. When a device having a 5 Volt power supply range controls the bus, the 3.3 V OCD's input/output (I/O) circuitry is subject to a signal on the bus having a magnitude of 5.0.+-.10% V.
The OCD of FIG. 5 employs a floating N-Well 40 in combination with over-voltage feedback to prevent current leakage into the 3.3 V supply voltage VDD, when in the high impedance (HIZ) state, and to prevent latch-up. Current leakage into the 3.3 V supply is prevented by feeding back an overvoltage (greater than 3.3 V+Vt.sub.PFET, where Vt.sub.PFET is the PFET threshold voltage) at DATA OUTPUT 24 to the gate of PFET 32 through PFETs 30 and 36. With the gate of PFET 32 at the same potential as DATA OUTPUT 24 and node B, PFET 32 is in the OFF state, and no DC current passes through PFET 32 into the 3.3 V supply. Voltage stress across the gate oxide of PFET 32 under these conditions is also eliminated. Placing the low-voltage OCD PFETs into a floating N-Well prevents the parasitic p-n junctions associated with the PFETs from becoming forward biased and potentially causing latch up when DATA OUTPUT 24 is driven higher than 3.3 V+V.sub.be, where V.sub.be is the turnon voltage of the parasitic p-n junction diodes and has a value of approximately 0.7 V DC and 1.0 V AC.
Adams et al. also describe the use of stacked NFETs (34 and 12, or 26 arid 22) with the gate node of NFETs 34 and 26 coupled to VDD (3.3 V). The stacked topology reduces device degradation due to hot-electron effects when discharging a node driven high by a higher voltage device coupled to the data bus. For example, DATA OUTPUT 24 can reach a most positive up level (MPUL) of 5.5 V. With the gate of NFET 26 coupled to VDD (3.3 V), the drain of NFET 22 can reach a voltage of 3.3 V-Vt.sub.NFET (about 2.9 V), where Vt.sub.NFET is the threshold voltage for the NFET. This results in a gate stress of about 2.2 V and about 2.9 V across NFETs 26 and 22 respectively, which is well within the 4.5 V maximum allowable stress.
Additional OCD protection methods are also known. Many include interfacing a lower-voltage technology circuit with a bus that also interfaces with higher voltage components, and use the following concepts:
1. The low-voltage technology circuit is only capable of driving a logic-high signal equal in magnitude to its core voltage (VDD); PA1 2. Over-voltage detection is accomplished with a PFET the gate electrode of which is tied to VDD of the lower-voltage technology; PA1 3. The over-voltage may be fed back through one or more PFETs to turn off the OCD PFET pull-up to prevent sinking DC current into the lower-voltage technology's power supply; PA1 4. The lower voltage technology employs the floating N-Well concept to prevent latch-up when the bus is being driven by a higher voltage device; and PA1 5. The NFET topology is as described by Adams et al.
Improved methods of protecting CMOS devices including, but not limited to, OCDs are desired.